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Layout engineer

Delft, The Netherlands

DESCRIPTION

At SystematIC we deliver excellence in advanced Analog and Mixed-signal SoC design with a focus on power conversion and sensor interface applications. To strengthen our team, we welcome a Layout engineer who can take a leading role in creating complex IC layouts. You have a passion for IC layouts, backed by professionalism and commitment to bring optimal solutions to our customers. You are fascinated by electronics and intend to continuously enhance your knowledge and capacities in this area. If creating optimal layouts motivates you, we encourage you to contact us.

RESPONSIBILITIES AND TASKS

  • Communicate with design engineers on layout trade-offs as needed to build complex analog and mixed signal block level layouts in Sub-Micron CMOS technologies
  • Deliver high quality analog block layouts that meet stringent matching, performance, area and power requirements while conforming to all PDV design requirements and meet project milestone deadlines
  • Running complete set of design verification tools available on block-level, Sub-System level, and top-level layouts
  • Provide accurate schedules for block level, top-level layout and integration and report to layout manager
  • Recognize failure prone circuit and layout structures and propose mitigating actions
  • Debug and drive resolutions to Physical Design Kit issues, DRC/LVS/ERC improvements with respect to layouts
  • Solve problems while using a combination of technical skills, intuition, and creativity
  • Contribute ideas for improved productivity and automation of layout tasks
  • Recognize apparent mistakes in the analog design
  • Propose design changes when it benefits the layout

EDUCATION AND EXPERIENCE

  • BSc or MSc degree Electrical engineering, specialized in Micro-electronics
  • 3+ years’ experience creating custom analog/mixed-signal layouts at chip, block, and device levels in sub-micron CMOS technologies
  • Expertise with Cadence Virtuoso XL schematic driven layout design flow, Virtuoso Floor Planning, Constraint Driven Layout, and extraction flows
  • Expertise using Cadence verification suite (PVS-DRC, LVS, ERC); high proficiency with interpretation, debug, and understanding of results
  • Strong experience with high performance analog layout techniques for device matching, common centroid layout, isolation, shielding, use of dummy devices, parasitic sensitivities, and also chip level electromigration, IR drop, self-heating, cross coupling capacitance and DFM practices
  • Good understanding of package needs and constraints with respect to chip level
  • Layout experience with analog on-top and digital on-top flows, including defining, directing, and reviewing layout team’s work
  • Proven capability at chip and block level in floor planning, power routing, ESD, physical design area estimates, effort/schedule estimations
  • Understanding of multiple voltage (HV) domains and layout techniques required
  • Custom analog layout experience should include various analog IP blocks: PLLs, OSC, ADC, DAC, LDO and Bandgap reference
  • Excellent communication skills and ability to work with cross-functional teams in a demanding team-oriented environment
  • Self-starter and self-sufficient in problem solving and accomplishing tasks
  • Experience with Analog design is highly appreciated
  • Scripting experience in PERL or SKILL CODE is considered a plus, but not required

BENEFITS

SystematIC offers a great working environment for talented, proactive and passionate people with diverse interesses and backgrounds. Our team shares a professional vision on integrated circuit design and product development and promotes a culture of openness, forward-thinking, problem solving and cooperation. We like to boost creativity and productivity in an open and inviting atmosphere.

We offer:

  • Inspiring, informal and open company culture
  • Good opportunities to work with teams from all over the world
  • Direct customer contact and growth in responsibility
  • Steady personal development within a flat organizational hierarchy
  • A competitive remuneration
  • 26 vacation days a year (with a 40-hour contract), good pension plan
  • The possibility to work from home (part-time)
  • Monthly corporate gatherings with drinks and food
  • Corporate events (at least twice a year)
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